iverilog

Verilog simulation and synthesis tool

Details

Homepage:

https://steveicarus.github.io/iverilog/

License:

GPL-2.0-or-later, LGPL-2.1-or-later

Maintainer:

Orphaned

Built at:

2023-11-13 07:57 - 2023-11-13 11:15

Source files:

https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz

Installed size:

6.47 MiB - 6.65 MiB

Popularity:

2 usages in 93 reports

Depending on:

• glibc>=2.36_{_1}
• libgcc>=4.4.0_{_1}
• libreadline8>=8.0_{_1}
• libstdc++>=4.4.0_{_1}
• musl>=1.1.24_{_7}
• zlib>=1.2.3_{_1}